Electronic devices, for example, memories have different power requirements in different states. Examples of different states include but are not limited to a standby state and an active state. A memory includes a power node which needs to be charged or powered when the memory transitions from one state to another. In 65 nanometer (nm) memory design, a Positive-channel metal oxide semiconductor (PMOS) is used as a switch to connect the power node with external power supply. During the standby mode the switch is off to reduce peripheral leakage. The PMOS used is of large size to provide current to the memory in active mode. When the memory is switched from standby state to active state the PMOS is turned ON. The turning ON of the large PMOS leads to surge current as the drain of the PMOS connected to the power node is at ground level and the source of the PMOS is at external power supply level. The surge current causes severe strain on the power supply and may even damage power supply. Further, the surge current generates heat and may lead to failure of the electronic devices. Moreover, the surge current also causes electrical migration due to presence of metal in the electronic devices. Therefore, a technique to minimize surge current during charging the power node is needed.
In a conventional method of minimizing surge current a delay chain is used to slow down charging the power node. FIG. 1 illustrates a prior art circuit 100 for charging a power node 110 of a memory 111 through a plurality of PMOS switches including a PMOS switch 105a, a PMOS switch 105b and a PMOS switch 105n. A delay chain 115 includes a plurality of inverter circuits including an inverter circuit 120a and an inverter circuit 120m connected in series to sequentially activate the plurality of PMOS switches in response to an input activation signal applied to PMOS switch 105a and inverter circuit 120a. The delay between activation of the nth PMOS switch and the (n+1)th PMOS switch is a few ten picoseconds. The number of inverters needed to avoid overloading power supply is proportional to current drain imposed by the memory at start-up, leading to increased area of a chip including the memory, which in turn increases cost. Moreover, in the chip with hundred of memories the input activation signal is a common signal. When the input activation signal is applied PMOS switch 105a of all the memories are turned ON simultaneously leading to huge current. Similarly, PMOS switch 105b, followed by other PMOS switches, of all the memories are turned ON simultaneously.
In light of the foregoing discussion, there is a need of an efficient technique for minimizing surge current during charging the power node.